PRI=high, TO_PER=to4, TO_CLKDIV=dis, DSTWD=byte, SRCWD=byte, DSTINC=dis, TO_WAIT=dis, SRCINC=dis, REQUEST=MEMTOMEM, DIS_IE=dis, RLDEN=dis, EN=dis, CTZ_IE=dis
DMA Channel Control Register.
| EN | Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. 0 (dis): Disable. 1 (en): Enable. |
| RLDEN | Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. 0 (dis): Disable. 1 (en): Enable. |
| PRI | DMA Priority. 0 (high): Highest Priority. 1 (medHigh): Medium High Priority. 2 (medLow): Medium Low Priority. 3 (low): Lowest Priority. |
| REQUEST | Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. 0 (MEMTOMEM): Memory To Memory 1 (SPI1RX): SPI1 RX 4 (UART0RX): UART0 RX 5 (UART1RX): UART1 RX 7 (I2C0RX): I2C0 RX 8 (I2C1RX): I2C1 RX 9 (ADC): ADC 10 (I2C2RX): I2C2 RX 12 (CSI2RX): CSI2 RX 13 (PCIFRX): PCIF RX 14 (UART2RX): UART2 RX 15 (SPI0RX): SPI0 RX 16 (AESRX): AES RX 30 (I2SRX): I2S RX 33 (SPI1TX): SPI1 TX 36 (UART0TX): UART0 TX 37 (UART1TX): UART1 TX 39 (I2C0TX): I2C0 TX 40 (I2C1TX): I2C1 TX 42 (I2C2TX): I2C2 TX 44 (CRCTX): CRC TX 46 (UART2TX): UART2 TX 47 (SPI0TX): SPI0 TX 48 (AESTX): AES TX 62 (I2STX): I2S TX |
| TO_WAIT | Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. 0 (dis): Disable. 1 (en): Enable. |
| TO_PER | Timeout Period Select. 0 (to4): Timeout of 3 to 4 prescale clocks. 1 (to8): Timeout of 7 to 8 prescale clocks. 2 (to16): Timeout of 15 to 16 prescale clocks. 3 (to32): Timeout of 31 to 32 prescale clocks. 4 (to64): Timeout of 63 to 64 prescale clocks. 5 (to128): Timeout of 127 to 128 prescale clocks. 6 (to256): Timeout of 255 to 256 prescale clocks. 7 (to512): Timeout of 511 to 512 prescale clocks. |
| TO_CLKDIV | Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. 0 (dis): Disable timer. 1 (div256): hclk / 256. 2 (div64k): hclk / 64k. 3 (div16M): hclk / 16M. |
| SRCWD | Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. 0 (byte): Byte. 1 (halfWord): Halfword. 2 (word): Word. |
| SRCINC | Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. 0 (dis): Disable. 1 (en): Enable. |
| DSTWD | Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). 0 (byte): Byte. 1 (halfWord): Halfword. 2 (word): Word. |
| DSTINC | Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. 0 (dis): Disable. 1 (en): Enable. |
| BURST_SIZE | Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. |
| DIS_IE | Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. 0 (dis): Disable. 1 (en): Enable. |
| CTZ_IE | Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. 0 (dis): Disable. 1 (en): Enable. |